The continuing advancement in semiconductor process technology enables packing larger amounts of memory on an integrated circuit die. Because of the large size of the memory, it is customary to break up the memory array into multiple banks, and access only the selected bank in a given memory access. In memory devices where charge pumps are needed in order to provide on-die supply voltages greater than that provided externally, multiple charge pumps are typically needed in order to provide the requisite amount of current. In conventional designs, these pumps are typically activated with no regard to the location of circuit blocks or memory banks that are activated in a given memory access. Either all pumps are activated at once, which can cause power surge and noise, or the pumps are activated in a predetermined sequence. In the latter case, if in a given access to the memory device, the first activated pump happens to be far from the selected memory bank, the time delay in the pump voltage reaching the selected memory bank can adversely impact the performance of the memory device.
Thus, there is a need for techniques to improve the manner in which charge pumps are activated in memory devices.